1. Field of the Invention
The present invention is related to an electrostatic discharge (ESD) detection circuit. In particular, the present invention relates to a system-level ESD detection circuit.
2. Description of the Prior Art
As the scale of devices in ICs has become smaller, the devices have become more vulnerable to Electrostatic discharge (ESD). Hence, ESD has been one of the most important reliability issues for IC products and must be taken into consideration in the design phase of all ICs.
To meet the component-level ESD reliability, many on-chip ESD protection circuits have been proposed and added to the I/O cells and power cells of CMOS ICs. However, besides the component-level ESD stress, system-level ESD issue is also an increasingly significant reliability issue in CMOS IC products. It has known that some CMOS ICs are very susceptible to system-level ESD stress, even though they have passed the component-level ESD specifications such as human-body-model (HBM) of ±2 kV, machine-model (MM) of ±200V, and charged-device-model (CDM) of ±1 kV.
The tendency of guarding against system-level ESD results from the strict requirements of certain reliability test standards, such as system-level ESD tests for electromagnetic compatibility (EMC) regulation. In system-level ESD tests, normal power is provided to the internal circuits of an IC and the internal circuits are operated to perform their default functions. The purpose of system-level ESD tests is to determine whether the internal circuits can keep normal operations even being interfered by ESD noises or whether the circuits can be automatically reset to recover themselves. In the system-level ESD test standard, IEC 61000-4-2, electronic products must sustain the ESD level of +8 kV under contact-discharge test and +15 kV under air-discharge test to meet the immunity requirement of “level 4.” High-energy ESD-induced noises often cause damage or malfunction of CMOS ICs inside the equipment under test (EUT).
FIG. 1 illustrates the connecting relationship of a system-level ESD detection circuit 16 and an internal circuit 14 in an IC chip. Under the normal power-on condition, a power-on/reset circuit 12 starts up the internal circuit 14 and resets the ESD detection circuit 16. Thereafter, the internal circuit 14 starts its default operations and the ESD detection circuit 16 starts to detect ESD events. Once a sudden voltage overshoot or undershoot happens on the power rail (VDD or VSS), the ESD detection circuit 16 will inform the power-on/reset circuit 12 to perform a protection procedure for the internal circuit 14. This protection procedure may be different in different ICs with various firmware or circuit designs. For instance, the power-on/reset circuit 12 might reset the whole or only one part of the internal circuit 14. By resetting certain circuits, more serious malfunction of the whole chip may be accordingly prevented.
“On-chip transient detection circuit for system-level ESD protection in CMOS integrated circuits to meet electromagnetic compatibility regulation” reported by M.-D. Ker, C.-C. Yen, and P.-C. Shih on IEEE Trans. Electromagnetic Compatibility, vol. 50, no. 1, pp. 1-9, February, 2008 has proposed a system-level ESD detection circuit. Please refer to FIG. 2, which illustrates the ESD detection circuit in the above paper. The capacitors CP1 and CP2 in FIG. 2 are respectively used for detecting fast transients happened on VDD and VSS when the system is subjected to ESD events.
Initially, the node A is reset to ground by providing a high-level pulse to the gate of the transistor MNR (i.e. the node labeled as Reset). Under the condition without ESD events, the output of the inverter INV3 has a low-level voltage. Once a positive ESD zapping is applied to the VDD power rail in FIG. 2 while the VSS power rail is grounded, the positive ESD voltage will be coupled through the capacitor CP1 and raise the voltage at the input of the inverter INV1 (consisting of MP1 and MN1). Accordingly, the output of the inverter INV3 will then have a high-level voltage. Thereby, a subsequent circuit (e.g. the power-on/reset circuit 12 in FIG. 1) can be aware of the ESD event.
Further, the inverters INV1 and INV2 form a latch to prolong the detected status so that the subsequent circuit can have enough time to respond to this condition. After the subsequent circuit has dealt with the ESD transient noise, the detection circuit in FIG. 2 can be reset again.
It can be seen that the detection circuit in prior arts can only detect ESD events but not the level of ESD voltages. The subsequent circuit in prior arts accordingly can only deal with all ESD events in the same manner instead of performing different measures in response to different ESD levels.